
Address: | Warsaw, Poland |
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Languages: | Polish (native), English (B2, fluent) |
Education: | M.Sc.Eng. in Computer Science |
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Contact: | ofers @ pawelczyk.it |
Able to take on critical components, devise the right solutions, achieve desired goals, lead tech toward success. Accumulated technical experience, mostly in embedded, but also in networking and FIPS 140. Maintained complex features and projects. Fosters deep understanding of topics. Works fully remote (globally) or on-site/hybrid (in Warsaw).
▸ Embedded software projects related to CPUs – microcode in SoCs for datacenters.
Maintained critical power management feature responsible for power limiting in Intel® Xeon® 6 product family: triaged issues, debugged and root caused problems, proposed and implemented solutions, thus accelerating feature maturity and reducing rate of misbehavior reports down to 0 despite lack of prior knowledge in this domain. Co-operated with architects and validators to improve time to response and stability of the feature. Enabled junior developer to successfully ramp up and contribute in such complex feature. Sped up 300x important step in the firmware build process.
▸ Hardware + embedded software projects related to non-volatile memory.
Led FIPS 140-3 readiness of firmware for in-house microcontroller and product using it, worked with NVLAP accredited CST lab, identified conformance gaps and helped define solutions, ultimately enabling cross-geo team to achieve Cryptographic Algorithm Validation Program (CAVP) validation, and march toward Entropy Source Validation (ESV) + Cryptographic Module Validation Program (CMVP) validation. Drove software/firmware-related improvements in FIPS 140-3 Implementation Guidance (IG) via external Cryptographic Module User Forum (CMUF) WG, better aligning it to industry needs. Effectively helped in path clearing vital FIPS 140-3 related topics for other projects in the company.
▸ Embedded software projects related to non-volatile memory – bootloader and firmware.
Developed non-patchable bootROM, early tested using in-house FPGA board with help of RTL engineers and FW validators. Sped up init code by 60%, thus substantially reducing simulation times of pre-silicon validation and immensely cutting gate level simulation times. Sped up flash programming during product Power-On phase by 10x via improving debug tools. Prepared and conducted training sessions to expand bootROM knowledge among firmware developers. Led local developers team further improving bootROM for next HW stepping of in-house microcontroller: converging cryptography implementations and strenghtening FIPS 140 readiness of bootROM/firmware. Co-operated with Pre-Si and Post-Si validators to maintain bug-free bootROM for each stepping (bugs could drive need for new stepping costing $1M+). Convinced stakeholders to invest in dry-run FIPS 140 operational test, established internal cross-geo WG preparing for and performing it, ultimately shifting left conformance tests and recognition of needed changes (deficiencies found early enough to address them before Tape-In for next stepping).